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1 ltc1196/ltc1198 s f ea t u re 8-bit, so-8, 1msps adcs with auto-shutdown options n high sampling rates: 1mhz (ltc1196) 750khz (ltc1198) n low cost n so-8 plastic package n single supply 3v and 5v specifications n low power: 10mw at 3v supply 50mw at 5v supply n auto-shutdown: 1na typical (ltc1198) n 1/2lsb total unadjusted error over temperature n 3-wire serial i/o n 1v to 5v input span range (ltc1196) n converts 1mhz inputs to 7 effective bits n differential inputs (ltc1196) n 2-channel mux (ltc1198) the ltc1196/ltc1198 are 600ns, 8-bit a/d converters with sampling rates up to 1mhz. they are offered in 8-pin so packages and operate on 3v to 6v supplies. power dissipation is only 10mw with a 3v supply or 50mw with a 5v supply. the ltc1198 automatically powers down to a typical supply current of 1na whenever it is not perform- ing conversions. these 8-bit switched-capacitor succes- sive approximation adcs include sample-and-holds. the ltc1196 has a differential analog input; the ltc1198 offers a software selectable 2-channel mux. the 3-wire serial i/o, so-8 packages, 3v operation and extremely high sample rate-to-power ratio make these adcs an ideal choice for compact, high speed systems. these adcs can be used in ratiometric applications or with external references. the high impedance analog inputs and the ability to operate with reduced spans below 1v full scale (ltc1196) allow direct connection to signal sources in many applications, eliminating the need for gain stages. the a grade devices are specified with total unadjusted error of 1/2lsb maximum over temperature. d u escriptio u s a o pp l ic at i n high speed data acquisition n disk drives n portable or compact instrumentation n low power or battery-operated systems u a o pp l ic at i ty p i ca l single 5v supply, 1msps, 8-bit sampling adc effective bits and s/(n + d) vs input frequency input frequency (hz) 1k s/(n + d) (db) 8 7 6 5 4 3 2 1 0 10k 100k 1m 1196/98 g24 50 44 effective number of bits (enobs) v ref = v cc = 2.7v f smpl = 383khz (ltc1196) f smpl = 287khz (ltc1198) v ref = v cc = 5v f smpl = 1mhz (ltc1196) f smpl = 750khz (ltc1198) t a = 25? 5v 1 m f analog input 0v to 5v range 1196/98 ta01 serial data link to asic, pld, mpu, dsp, or shift registers ?n gnd v cc clk d out +in cs 1 2 3 4 8 7 6 5 ltc1196 (so-8) v ref
2 ltc1196/ltc1198 a u g w a w u w a r b s o lu t exi t i s (notes 1, 2) supply voltage (v cc ) to gnd .................................... 7v voltage analog reference ...................... C0.3v to v cc + 0.3v digital inputs .......................................... C0.3v to 7v digital outputs .......................... C0.3v to v cc + 0.3v power dissipation ............................................. 500mw operating temperature range ltc1196-1ac, ltc1198-1ac, ltc1196-1bc, ltc1198-1bc, ltc1196-2ac, ltc1198-2ac, ltc1196-2bc, ltc1198-2bc................ 0 c to 70 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................ 300 c ltc1196-1 ltc1196-2 ltc1198-1 ltc1198-2 symbol parameter conditions min typ max min typ max units v cc supply voltage 2.7 6 2.7 6 v v cc = 5v operation f clk clock frequency 0.01 14.4 0.01 12.0 mhz l 0.01 12.0 0.01 9.6 mhz t cyc total cycle time ltc1196 12 12 clk ltc1198 16 16 clk t smpl analog input sampling time 2.5 2.5 clk t hcs hold time cs low after last clk - 10 13 ns t sucs setup time cs before first clk - 20 26 ns (see figures 1, 2) t hdi hold time d in after clk - ltc1198 20 26 ns wu u package / o rder i for atio order part number* ltc1196-1acs8 ltc1196-1bcs8 ltc1196-2acs8 ltc1196-2bcs8 1961a 1961b 1962a 1962b s8 part marking order part number* LTC1198-1ACS8 ltc1198-1bcs8 ltc1198-2acs8 ltc1198-2bcs8 s8 part marking 1981a 1981b 1982a 1982b * parts available in n8 package. consult factory for n8 samples. 1 2 3 4 8 7 6 5 top view v cc (v ref ) clk d out d in ch0 ch1 gnd s8 package 8-lead plastic soic cs/ shutdown t jmax = 150 c, q ja = 175 c/w t jmax = 150 c, q ja = 175 c/w 1 2 3 4 8 7 6 5 top view v cc clk d out v ref s8 package 8-lead plastic soic cs +in ?n gnd reco e ded operati g co ditio s w u w u u u
3 ltc1196/ltc1198 reco e ded operati g co ditio s w u w u u u ltc1196-1 ltc1196-2 ltc1198-1 ltc1198-2 symbol parameter conditions min typ max min typ max units co verter a d ultiplexer characteristics uu w e lectr ic al c c hara ter st ics digital a d u i dc v cc = 5v, v ref = 5v, unless otherwise noted. C 0.05v to v cc + 0.05v t sudi setup time d in stable before clk - ltc1198 20 26 ns t whclk clk high time f clk = f clk(max) 40% 40% 1/f clk t wlclk clk low time f clk = f clk(max) 40% 40% 1/f clk t whcs cs high time between data transfer cycles 25 32 ns t wlcs cs low time during data transfer ltc1196 11 11 clk ltc1198 15 15 clk v cc = 5v, v ref = 5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. ltc1196-xa ltc1196-xb ltc1198-xa ltc1198-xb parameter conditions min typ max min typ max units no missing codes resolution l 8 8 bits offset error l 1/2 1 lsb linearity error (note 3) l 1/2 1 lsb full-scale error l 1/2 1 lsb total unadjusted error (note 4) ltc1196, v ref = 5.000v l 1/2 1 lsb ltc1198, v cc = 5.000v analog and ref input range ltc1196 v analog input leakage current (note 5) l 1 1 m a symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.0 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 4.75v, i o = 10 m a l 4.5 4.74 v v cc = 4.75v, i o = 360 m a l 2.4 4.71 v v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz hi-z output leakage cs = high l 3 m a i source output source current v out = 0v C 25 ma i sink output sink current v out = v cc 45 ma i ref reference current, ltc1196 cs = v cc l 0.001 3 m a f smpl = f smpl(max) l 0.5 1 ma i cc supply current cs = v cc , ltc1198 (shutdown) l 0.001 3 m a cs = v cc , ltc1196 l 715 ma f smpl = f smpl(max), ltc1196/ltc1198 l 11 20 ma
4 ltc1196/ltc1198 v cc = 5v, v ref = 5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. dy a ic accuracy u w reco e ded operati g co ditio s w u w u u u ac characteristics v cc = 5v, v ref = 5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. v cc = 2.7v operation ltc1196 ltc1198 symbol parameter conditions min typ max min typ max units s/(n + d) signal-to-noise plus distortion 500khz/1mhz input signal 47/45 47/45 db thd total harmonic distortion 500khz/1mhz input signal 49/47 49/47 db peak harmonic or spurious noise 500khz/1mhz input signal 55/48 55/48 db imd intermodulation distortion f in1 = 499.37khz, 51 51 db f in2 = 502.446khz full power bandwidth 8 8 mhz full linear bandwidth [s/(n + d) > 44db] 1 1 mhz ltc1196-1 ltc1196-2 ltc1198-1 ltc1198-2 symbol parameter conditions min typ max min typ max units f clk clock frequency 0.01 5.4 0.01 4 mhz l 0.01 4.6 0.01 3 mhz t cyc total cycle time ltc1196 12 12 clk ltc1198 16 16 clk t smpl analog input sampling time 2.5 2.5 clk t hcs hold time cs low after last clk - 20 40 ns t sucs setup time cs before first clk - 40 78 ns (see figures 1, 2) ltc1196-1 ltc1196-2 ltc1198-1 ltc1198-2 symbol parameter conditions min typ max min typ max units t conv conversion time (see figures 1, 2) 600 710 ns l 710 900 ns f smpl(max) maximum sampling frequency ltc1196 1.20 1.00 mhz ltc1196 l 1.00 0.80 mhz ltc1198 0.90 0.75 mhz ltc1198 l 0.75 0.60 mhz t ddo delay time, clk - to d out data valid c load = 20pf 55 64 68 78 ns l 73 94 ns t dis delay time cs - to d out hi-z l 70 120 88 150 ns t en delay time, clk to d out enabled c load = 20pf l 30 50 43 63 ns t hdo time output data remains valid c load = 20pf l 30 45 30 55 ns after clk - t r d out fall time c load = 20pf l 515 1020 ns t f d out rise time c load = 20pf l 515 1020 ns c in input capacitance analog input on channel 30 30 pf analog input off channel 5 5 pf digital input 5 5 pf
5 ltc1196/ltc1198 reco e ded operati g co ditio s w u w u u u v cc = 2.7v operation co verter a d ultiplexer characteristics uu w v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. e lectr ic al c c hara ter st ics digital a d u i dc v cc = 2.7v, v ref = 2.5v, unless otherwise noted. C 0.05v to v cc + 0.05v ltc1196-1 ltc1196-2 ltc1198-1 ltc1198-2 symbol parameter conditions min typ max min typ max units t hdi hold time d in after clk - ltc1198 40 78 ns t sudi setup time d in stable before clk - ltc1198 40 78 ns t whclk clk high time f clk = f clk(max) 40% 40% 1/f clk t wlclk clk low time f clk = f clk(max) 40% 40% 1/f clk t whcs cs high time between data transfer cycles 50 96 ns t wlcs cs low time during data transfer ltc1196 11 11 clk ltc1198 15 15 clk symbol parameter conditions min typ max units v ih high level input voltage v cc = 3.6v l 1.9 v v il low level input voltage v cc = 2.7v l 0.45 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C2.5 m a v oh high level output voltage v cc = 2.7v, i o = 10 m a l 2.3 2.60 v v cc = 2.7v, i o = 360 m a l 2.1 2.45 v v ol low level output voltage v cc = 2.7v, i o = 400 m a l 0.3 v i oz hi-z output leakage cs = high l 3 m a i source output source current v out = 0v C 10 ma i sink output sink current v out = v cc 15 ma i ref reference current, ltc1196 cs = v cc l 0.001 3.0 m a f smpl = f smpl(max) l 0.25 0.5 ma i cc supply current cs = v cc = 3.3v, ltc1198 (shutdown) l 0.001 3.0 m a cs = v cc = 3.3v, ltc1196 l 1.5 4.5 ma f smpl = f smpl(max), ltc1196/ltc1198 l 2.0 6.0 ma ltc1196-xa ltc1196-xb ltc1198-xa ltc1198-xb parameter conditions min typ max min typ max units no missing codes resolution l 8 8 bits offset error l 1/2 1 lsb linearity error (note 3) l 1/2 1 lsb full-scale error l 1/2 1 lsb total unadjusted error (note 4) ltc1196, v ref = 2.500v l 1/2 1 lsb ltc1198, v cc = 2.700v analog and ref input range ltc1196 v analog input leakage current (note 5) l 1 1 m a
6 ltc1196/ltc1198 dy a ic accuracy u w v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. ac characteristics v cc = 2.7v, v ref = 2.5v, f clk = f clk(max) as defined in recommended operating conditions, unless otherwise noted. the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 4: total unadjusted error includes offset, full scale, linearity, multiplexer and hold step errors. note 5: channel leakage current is measured after the channel selection. ltc1196-1 ltc1196-2 ltc1198-1 ltc1198-2 symbol parameter conditions min typ max min typ max units t conv conversion time (see figures 1, 2) 1.58 2.13 m s l 1.85 2.84 m s f smpl(max) maximum sampling frequency ltc1196 450 333 khz ltc1196 l 383 250 khz ltc1198 337 250 khz ltc1198 l 287 187 khz t ddo delay time, clk - to d out data valid c load = 20pf 100 150 130 200 ns l 180 250 ns t dis delay time cs - to d out hi-z l 110 220 120 250 ns t en delay time, clk to d out enabled c load = 20pf l 80 130 100 200 ns t hdo time output data remains valid c load = 20pf l 45 90 45 120 ns after clk - t r d out fall time c load = 20pf l 10 30 15 40 ns t f d out rise time c load = 20pf l 10 30 15 40 ns c in input capacitance analog input on channel 30 30 pf analog input off channel 5 5 pf digital input 5 5 pf ltc1196 ltc1198 symbol parameter conditions min typ max min typ max units s/(n + d) signal-to-noise plus distortion 190khz/380khz input signal 47/45 47/45 db thd total harmonic distortion 190khz/380khz input signal 49/47 49/47 db peak harmonic or spurious noise 190khz/380khz input signal 53/46 53/46 db imd intermodulation distortion f in1 = 189.37khz, 51 51 db f in2 = 192.446khz full power bandwidth 5 5 mhz full linear bandwidth [s/(n + d) > 44db] 0.5 0.5 mhz
7 ltc1196/ltc1198 frequency (mhz) 0 supply current (ma) 12 9 8 7 6 5 4 3 2 1 0 1196/98 g01 216 468 10 14 t a = 25? cs = 0v v ref = v cc v cc = 5v v cc = 2.7v supply current vs clock rate supply current vs supply voltage supply current vs sample rate cc hara terist ics uw a t y p i ca lper f o r c e temperature (?) ?5 supply current (ma) 10 9 8 7 6 5 4 3 2 1 0 ?5 25 45 125 1196/98 g04 ?5 5 65 85 105 cs = 0v v cc = 5v v cc = 2.7v supply current vs temperature offset vs reference voltage offset vs supply voltage linearity error vs reference voltage linearity error vs supply voltage supply voltage (v) 2.5 magnitude of offset (lsb) 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 3.5 4.5 5.0 1196/98 g06 3.0 4.0 5.5 6.0 t a = 25? v ref = v cc f clk = 3mhz reference voltage (v) linearity error (lsb) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1196/98 g07 0.5 5.0 3.5 2.5 4.0 1.0 2.0 1.5 4.5 3.0 t a = 25? v cc = 5v f clk = 12mhz supply voltage (v) 2.5 linearity error (lsb) 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 3.5 4.5 5.0 1196/98 g08 3.0 4.0 5.5 6.0 t a = 25? v ref = v cc f clk = 3mhz gain error vs reference voltage supply voltage (v) 2.5 14 12 10 8 6 4 2 0 4.0 5.0 1196/98 g02 3.0 3.5 4.5 5.5 6.0 supply current (ma) t a = 25? 0.000002 ltc1196 ltc1198 ?ctive?mode cs = 0v ?hutdown?mode cs = v cc ltc1198 sample rate (hz) 0.01 supply current (ma) 0.1 1 10 100 10k 100k 1196/98 g03 0.001 1k 1m lt1196 v cc = 5v lt1196 v cc = 2.7v lt1198 v cc = 5v lt1198 v cc = 2.7v t a = 25? reference voltage (v) 0.5 magnitude of offset (lsb = v ref ) 5.0 1196/98 g05 3.5 2.5 4.0 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.0 2.0 1.5 4.5 3.0 t a = 25? v cc = 5v f clk = 12mhz 1 256 reference voltage (v) 0 magnitude of gain error (lsb) 4.0 1196/98 g09 1.0 2.0 3.0 5.0 0.5 1.5 2.5 3.5 4.5 t a = 25? v cc = 5v f clk = 12mhz 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5
8 ltc1196/ltc1198 cc hara terist ics uw a t y p i ca lper f o r c e maximum clock frequency vs supply voltage gain vs supply voltage supply voltage (v) 2.5 magnitude of gain error (lsb) 0.5 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 0.5 3.5 4.5 5.0 1196/98 g10 3.0 4.0 5.5 6.0 t a = 25? f clk = 3mhz v ref = v cc supply voltage (v) 2.5 19 17 15 13 11 9 7 5 4.0 5.0 1196/98 g11 3.0 3.5 4.5 5.5 6.0 maximum clock frequency (mhz) t a = 25? v ref = v cc maximum clock frequency vs source resistance adc noise vs reference and supply voltage sample-and-hold acquisition time vs source resistance digital input logic threshold vs supply voltage d out delay time vs supply voltage d out delay time vs temperature source resistance ( w ) clock frequency (mhz) 18 16 14 12 10 8 6 4 2 0 1 100 1k 100k 1196/98 g12 10 10k t a = 25? v cc = v ref = 5v r source v in +in ?n temperature (?) ?5 minimum clock frequency (khz) 100 90 80 70 60 50 40 30 20 10 0 ?5 25 45 125 1196/98 g13 ?5 5 65 85 105 v cc = 5v v ref = 5v source resistance ( w ) 1 100 s&h acquisition time (ns) 1000 10000 100 10k 1196/98 g15 10 1k t a = 25? v cc = v ref = 5v r source + v in +in ?n temperature (?) ?0 d out delay time, t ddo (ns) 160 140 120 100 80 60 40 20 0 100 1196/98 g18 ?0 20 60 140 ?0 0 40 80 120 v cc = 5v v ref = v cc v cc = 2.7v supply voltage (v) 2.5 140 120 100 80 60 40 20 0 4.0 5.0 1196/98 g17 3.0 3.5 4.5 5.5 6.0 d out delay time, t ddo (ns) t a = 25? v ref = v cc supply voltage (v) 2.5 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 4.0 5.0 1196/98 g16 3.0 3.5 4.5 5.5 6.0 logic threshold (v) t a = 25? *as the frequency is decreased from 12mhz, minimum clock frequency ( d error 0.1lsb) represents the frequency at which a 0.1lsb shift in any code transition from its 12mhz value is first detected. minimum clock rate for 0.1lsb* error supply voltage (v) 2.5 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 4.0 5.0 1196/98 g14 3.0 3.5 4.5 5.5 6.0 peak-to-peak adc noise (lsb) t a = 25? v ref = v cc
9 ltc1196/ltc1198 cc hara terist ics uw a t y p i ca lper f o r c e temperature (?) ?0 leakage current (na) 1000 100 10 1 0.1 0.01 100 1196/98 g19 ?0 20 60 140 ?0 0 40 80 120 v cc = 5v v ref = 5v on channel off channel input channel leakage current vs temperature effective bits and s/(n + d) vs input frequency code 0 inl error (lsb) 0.5 64 128 160 1196/98 g22 32 96 192 224 256 0 0.5 v cc = 2.7v v ref = 2.5v f clk = 3mhz integral nonlinearity vs code at 2.7v input frequency (hz) 1k s/(n + d) (db) 8 7 6 5 4 3 2 1 0 10k 100k 1m 1196/98 g24 50 44 effective number of bits (enobs) v ref = v cc = 2.7v f smpl = 383khz (ltc1196) f smpl = 287khz (ltc1198) v ref = v cc = 5v f smpl = 1mhz (ltc1196) f smpl = 750khz (ltc1198) t a = 25? 4096 point fft plot at 5v frequency (khz) 0 0 10 20 30 40 50 60 70 80 90 100 400 1196/98 g25 100 200 300 500 v cc = 5v f in = 29khz f smpl = 882khz magnitude (db) 4096 point fft at 2.7v frequency (khz) 0 0 10 20 30 40 50 60 70 80 90 100 150 1196/98 g26 50 100 200 v cc = 2.7v f in = 29khz f smpl = 340khz magnitude (db) fft output of 455khz am signal digitized at 1msps frequency (khz) 0 0 10 20 30 40 50 60 70 80 90 100 400 1196/98 g27 100 200 300 500 v cc = 5v f in = 455khz with 20khz am f smpl = 1mhz magnitude (db) integral nonlinearity vs code at 5v code 0 integral nonlinearity error (lsb) 0.5 64 128 160 1196/98 g20 32 96 192 224 256 0 0.5 v cc = 5v v ref = 5v f clk = 12mhz differential nonlinearity vs code at 5v code 0 differential nonlinearity error (lsb) 0.5 64 128 160 1196/98 g21 32 96 192 224 256 0 0.5 v cc = 5v v ref = 5v f clk = 12mhz differential nonlinearity vs code at 2.7v code 0 differential nonlinearity error (lsb) 0.5 64 128 160 1196/98 g23 32 96 192 224 256 0 0.5 v cc = 2.7v v ref = 2.5v f clk = 3mhz
10 ltc1196/ltc1198 cc hara terist ics uw a t y p i ca lper f o r c e ripple frequency (hz) 1k 0 10 20 30 40 50 60 ?0 10k 100k 1m 1196/98 g28 feedthrough (db) t a = 25? v cc (v ripple = 20mv) f clk = 12mhz power supply feedthrough vs ripple frequency s/(n + d) vs reference voltage and input frequency reference voltage (v) 1.25 signal to noise plus distortion (db) 50 45 40 35 30 25 2.75 3.75 5.25 1196/98 g30 - 1.75 2.25 3.25 4.25 4.75 f in = 100khz v cc = 5v f in = 500khz f in = 200khz ripple frequency (hz) 1k 0 10 20 30 40 50 60 ?0 10k 100k 1m 1196/98 g29 feedthrough (db) t a = 25? v cc (v ripple = 10mv) f clk = 5mhz power supply feedthrough vs ripple frequency intermodulation distortion at 5v frequency (khz) 0 0 10 20 30 40 50 60 70 80 90 100 300 1196/98 g32 100 200 400 v cc = 5v f1 = 200khz f2 = 210khz f smpl = 750khz magnitude (db) input level (db) ?0 signal to noise-plus-distortion (db) 50 40 30 20 10 0 25 15 0 1196/98 g33 ?5 30 ?0 ?0 5 v ref = v cc = 5v f in = 500khz f smpl = 1mhz s/(n + d) vs input level frequency (khz) 0 0 10 20 30 40 50 60 70 80 90 100 200 1196/98 g31 50 100 150 250 v cc = 2.7v f1 = 100khz f2 = 110khz f smpl = 420khz magnitude (db) intermodulation distortion at 2.7v frequency (hz) 1k 70 60 50 40 30 20 10 0 1m 1196/98 g35 10k 100k 10m spurious-free dynamic range (db) t a = 25? v cc = 3v f clk = 5mhz v cc = 5v f clk = 12mhz spurious-free dynamic range vs frequency input frequency (hz) 1k peak-to-peak output (%) 10m 1196/98 g34 10k 100k 1m 100 80 60 40 20 0 v ref = v cc = 2.7v v ref = v cc = 5v output amplitude vs input frequency
11 ltc1196/ltc1198 pi fu ctio s u uu ltc1196 cs (pin 1): chip select input. a logic low on this input enables the ltc1196. a logic high on this input disables the ltc1196. in + (pin 2): analog input. this input must be free of noise with respect to gnd. in C (pin 3): analog input. this input must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. v ref (pin 5): reference input. the reference input defines the span of the a/d converter and must be kept free of noise with respect to gnd. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer. v cc (pin 8): power supply voltage. this pin provides power to the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane. ltc1198 cs/shutdown (pin 1): chip select input. a logic low on this input enables the ltc1198. a logic high on this input disables the ltc1198 and disconnects the power to the ltc1198. cho (pin 2): analog input. this input must be free of noise with respect to gnd. ch1 (pin 3): analog input. this input must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. d in (pin 5): digital data input. the multiplexer address is shifted into this input. d out (pin 6): digital data output. the a/d conversion result is shifted out of this output. clk (pin 7): shift clock. this clock synchronizes the serial data transfer. v cc (v ref )(pin 8): power supply and reference voltage. this pin provides power and defines the span of the a/d converter. it must be kept free of noise and ripple by bypassing directly to the analog ground plane. w i dagra b l o c k + c smpl bias and shutdown circuit serial port v cc (v cc /v ref ) clk d out in + (ch0) in (ch1) high speed comparator capacitive dac sar v ref (d in ) gnd pin names in parentheses refer to the ltc1198 cs (cs/shutdown) 1196/98 bd
12 ltc1196/ltc1198 test circuits d out waveform 1 (see note 1) v ih t dis 90% 10% d out waveform 2 (see note 2) cs note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. 1196/98 tc06 voltage waveforms for t dis on and off channel leakage current 5v a a i off i on polarity off channel on channel 1196/98 tc01 ? ? ? load circuit for t ddo , t r and t f d out 1.4v 3k 100pf test point 1196/98 tc02 load circuit for t dis and t en d out 3k 20pf test point v cc t dis waveform 2, t en t dis waveform 1 1196/98 tc05 voltage waveform for d out rise and fall times, t r , t f d out v ol v oh t r t f 1196/98 tc04 voltage waveform for d out delay time, t ddo and t hdo clk d out t ddo 1196/98 tc03 v ih t hdo v oh v ol
13 ltc1196/ltc1198 test circuits voltage waveforms for t en 1196/98 tc07 cs ltc1196 1 clk d out t en b7 v ol 23 4 1234 5 ltc1198 d in clk start d out t en b7 v ol 1196/98 tc08 cs 67 voltage waveforms for t en
14 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio overview the ltc1196/ltc1198 are 600ns sampling 8-bit a/d converters packaged in tiny 8-pin so packages and oper- ating on 3v to 6v supplies. the adcs draw only 10mw from a 3v supply or 50mw from a 5v supply. both the ltc1196 and the ltc1198 contain an 8-bit, switched-capacitor adc, a sample-and-hold, and a serial port (see block diagram). the on-chip sample-and-holds have full-accuracy input bandwidths of 1mhz. although they share the same basic design, the ltc1196 and ltc1198 differ in some respects. the ltc1196 has a differential input and has an external reference input pin. it can measure signals floating on a dc common-mode voltage and can operate with reduced spans below 1v. the ltc1198 has a 2-channel input multiplexer and can con- vert either channel with respect to ground or the difference between the two. it also automatically powers down when not performing conversion, drawing only leakage current. serial interface the ltc1196/ltc1198 will interface via three or four wires to asics, plds, microprocessors, dsps, or shift registers (see operating sequence in figures 1 and 2). to run at their fastest conversion rates (600ns), they must be clocked at 14.4mhz. hc logic families and any high speed asic or pld will easily interface to the adcs at that speed (see data transfer and typical application sections). full speed operation from a 3v supply can still be achieved with 3v asics, plds or hc logic circuits. figure 2. ltc1198 operating sequence example: differential inputs (ch 1, ch 0) figure 1. ltc1196 operating sequence 1196/98 f02 clk cs power down d in sgl/ diff dummy b3 b4 b5 b6 b7 null bits hi-z d out t smpl (2.5clks) hi-z start odd/ sign don? care b0* b2 b1 *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely. t sucs t cyc (16 clks) dummy t ddo t conv (8.5clks) clk cs b1 b2 b3 b4 b5 b6 b7 null bits hi-z d out 1196/98 f01 hi-z t sucs *after completing the data transfer, if further clocks are applied with cs low, the adc will output zeros indefinitely. b0* t cyc (12 clks) t ddo null bits b0 t smpl t conv (8.5 clks) t smpl
15 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio connection to a microprocessor or a dsp serial port is quite simple (see data transfer section). it requires no additional hardware, but the speed will be limited by the clock rate of the microprocessor or the dsp which limits the conversion time of the ltc1196/ltc1198. data transfer data transfer differs slightly between the ltc1196 and the ltc1198. the ltc1196 interfaces over 3 lines: cs, clk and d out . a falling cs initiates data transfer as shown in the ltc1196 operating sequence. after cs falls, the first clk pulse enables d out . after two null bits, the a/d conversion result is output on the d out line. bringing cs high resets the ltc1196 for the next data exchange. the ltc1198 can transfer data with 3 or 4 wires. the additional input, d in , is used to select the 2-channel mux configuration. the data transfer between the ltc1198 and the digital systems can be broken into two sections: input data word and a/d conversion result. first, each bit of the input data word is captured on the rising clk edge by the ltc1198. second, each bit of the a/d conversion result on the d out line is updated on the rising clk edge by the ltc1198. this bit should be captured on the next rising clk edge by the digital systems (see a/d conversion result section). data transfer is initiated by a falling chip select (cs) signal as shown in the ltc1198 operating sequence. after cs falls the ltc1198 looks for a start bit. after the start bit is received, the 4-bit input word is shifted into the d in input. the first two bits of the input word configure the ltc1198. the last two bits of the input word allow the adc to acquire the input voltage by 2.5 clocks before the conversion starts. after the conversion starts, two null bits and the conversion result are output on the d out line. at the end of the data exchange cs should be brought high. this resets the ltc1198 in preparation for the next data ex- change. input data word the ltc1196 requires no d in word. it is permanently configured to have a single differential input. the conver- sion result is output on the d out line in an msb-first sequence, followed by zeros indefinitely if clocks are continuously applied with cs low. the ltc1198 clocks data into the d in input on the rising edge of the clock. the input data word is defined as follows: start bit the first logical one clocked into the d in input after cs goes low is the start bit. the start bit initiates the data transfer. the ltc1198 will ignore all leading zeros which precede this logical one. after the start bit is received, the remaining bits of the input word will be clocked in. further inputs on the d in pin are then ignored until the next cs cycle. multiplexer (mux) address the 2 bits of the input word following the start bit assign the mux configuration for the requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following table. in single-ended mode, all input channels are measured with respect to gnd. d in1 d in2 d out1 d out2 cs shift mux address in 2 null bits shift a/d conversion result out 1196/98 ai01 sgl/ diff odd/ sign dummy start mux address dummy bits 119698 ai02 dummy ltc1198 channel selection mux address sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + 1 + ? + gnd ? ? single-ended mux mode differential mux mode 1196/98 ai03
16 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio dummy bits the last 2 bits of the input word following the mux address are dummy bits. either bit can be a logical one or a logical zero. these 2 bits allow the adc 2.5 clocks to acquire the input signal after the channel selection. a/d conversion result both the ltc1196 and the ltc1198 have the a/d conversion result appear on the d out line after two null bits (see operating sequence in figures 1 and 2). data on the d out line is updated on the rising edge of the clk line. the d out data should also be captured on the rising clk edge by the digital systems. data on the d out line remains valid for a minimum time of t hdo (30ns at 5v) to allow the capture to occur (see figure 3). figure 3. voltage waveform for d out delay time, t ddo and t hdo unipolar transfer curve the ltc1196/ltc1198 are permanently configured for unipolar only. the input span and code assignment for this conversion type are shown in the following figures. unipolar transfer curve unipolar output code output code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? ? 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 input voltage v ref ?1lsb v ref ?2lsb ? ? ? 1lsb 0v input voltage (v ref = 5.000v) 4.9805v 4.9609v ? ? ? 0.0195v 0v 1196/98 ai05 operation with d in and d out tied together the ltc1198 can be operated with d in and d out tied together. this eliminates one of the lines required to communicate to the digital systems. data is transmitted in both directions on a single wire. the pin of the digital systems connected to this data line should be configurable as either an input or an output. the ltc1198 will take control of the data line and drive it low on the 5th falling clk edge after the start bit is received (see figure 4). therefore the port line of the digital systems must be switched to an input before this happens to avoid a conflict. reducing power consumption the ltc1196/ltc1198 can sample at up to a 1mhz rate, drawing only 50mw from a 5v supply. power consump- tion can be reduced in two ways. using a 3v supply lowers the power consumption on both devices by a factor of five, to 10mw. the ltc1198 can reduce power even further because it shuts down whenever it is not converting. figure 5 shows the supply current versus sample rate for the ltc1196 and ltc1198 on 3v and 5v. to achieve such a low power consumption, especially for the ltc1198, several things must be taken into consideration. shutdown (ltc1198) figure 2 shows the operating sequence of the ltc1198. the converter draws power when the cs pin is low and powers itself down when that pin is high. for lowest power consumption in shutdown, the cs pin should be driven with cmos levels (0v to v cc ) so that the cs input buffer of the converter will not draw current. 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 ? ? 1196/98 ai04 clk d out t ddo 1196/98 tc03 v ih t hdo v oh v ol
17 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio figure 4. ltc1198 operation with d in and d out tied together sample rate (hz) 0.01 supply current (ma) 0.1 1 10 100 10k 100k 1196/98 f05 0.001 1k 1m lt1196 v cc = 5v lt1196 v cc = 2.7v lt1198 v cc = 5v lt1198 v cc = 2.7v figure 5. supply current vs sample rate for ltc1196/ ltc1198 operating on 5v and 2.7v supplies minimize cs low time (ltc1198) in systems that have significant time between conver- sions, lowest power drain will occur with the minimum cs low time. bringing cs low, transfering data as quickly as possible, then bringing it back high will result in the lowest current drain. this minimizes the amount of time the device draws power. operating on other than 5v supplies the ltc1196/ltc1198 operate from single 2.7v to 6v supplies. to operate the ltc1196/ltc1198 on other than 5v supplies, a few things must be kept in mind. input logic levels the input logic levels of cs, clk and d in are made to meet ttl on 5v supply. when the supply voltage varies, the input logic levels also change (see typical curve of digital input logic threshold vs supply voltage). for these two adcs to sample and convert correctly, the digital inputs have to be in the logical low and high relative to the operating supply voltage. if achieving micropower consumption is desirable on the ltc1198, the digital inputs must go rail-to-rail between supply voltage and ground (see reducing power consumption section). when the cs pin is high (= supply voltage), the ltc1198 is in shutdown mode and draws only leakage current. the status of the d in and clk input has no effect on the supply current during this time. there is no need to stop d in and clk with cs = high; they can continue to run without drawing current. 1 2 3 4 clk data (d in /d out ) start sgl/diff odd/sign dummy b7 b6 dummy bits latched by ltc1198 ltc1198 controls data line and sends a/d result back to the digital system the digital system controls data line and sends mux address to ltc1198 the digital system must release data line after 5th rising clk and before the 5th falling clk ltc1198 takes control of data line on 5th falling clk cs 1196/98 f04 5 dummy
18 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio clock frequency the maximum recommended clock frequency is 14.4mhz at 25 c for the ltc1196/ltc1198 running off a 5v supply. with the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve of maximum clock rate vs supply voltage). if the supply is reduced, the clock rate must be reduced also. at 3v the devices are specified with a 5.4mhz clock at 25 c. mixed supplies it is possible to have a digital system running off a 5v supply and communicate with the ltc1196/ltc1198 operating on a 3v supply. achieving this reduces the outputs of d out from the adcs to toggle the equivalent input of the digital system. the cs, clk and d in inputs of the adcs will take 5v signals from the digital system without causing any problem (see typical curve of digital input logic threshold vs supply voltage). with the ltc1196 operating on a 3v supply, the output of d out only goes between 0v and 3v. this signal easily meets ttl levels (see figure 6). figure 6. interfacing a 3v powered ltc1196 to a 5v system the v cc pin should be bypassed to the ground plane with a 1 m f tantalum with leads as short as possible. if the power supply is clean, the ltc1196/ltc1198 can also operate with smaller 0.1 m f surface mount or ceramic bypass capacitors. all analog inputs should be referenced directly to the single-point ground. digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. sample-and-hold both the ltc1196 and the ltc1198 provide a built-in sample-and-hold (s&h) function to acquire the input signal. the s&h acquires the input signal from + input during t smpl as shown in figures 1 and 2. the s&h of the ltc1198 can sample input signals in either single-ended or differential mode (see figure 7). single-ended inputs the sample-and-hold of the ltc1198 allows conversion of rapidly varying signals. the input voltage is sampled during the t smpl time as shown in figure 7. the sampling interval begins as the bit preceding the first dummy bit is shifted in and continues until the falling clk edge after the second dummy bit is received. on this falling edge, the s&h goes into hold mode and the conversion begins. differential inputs with differential inputs, the adc no longer converts just a single voltage but rather the difference between two volt- ages. in this case, the voltage on the selected + input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. however, the volt- age on the selected C input must remain constant and be free of noise and ripple throughout the conversion time. otherwise, the differencing operation may not be per- formed accurately. the conversion time is 8.5 clk cycles. therefore, a change in the C input voltage during this interval can cause conversion errors. for a sinusoidal voltage on the C input, this error would be: v error (max) = v peak 2 p f(C) 8.5/ f clk where f(C) is the frequency of the C input voltage, v peak is its peak amplitude and f clk is the frequency of the board layout considerations grounding and bypassing the ltc1196/ltc1198 are easy to use if some care is taken. they should be used with an analog ground plane and single-point grounding techniques. the gnd pin should be tied directly to the ground plane. 3v 4.7 m f mpu (e.g., 8051) 5v p1.4 p1.3 p1.2 1196/98 f06 differential inputs common-mode range 0v to 3v 3v v cc clk d out v ref ltc1196 ?n gnd +in cs
19 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio clk. v error is proportional to f(C) and inversely pro- portional to f clk . for a 60hz signal on the C input to generate a 1/4lsb error (5mv) with the converter running at clk = 12mhz, its peak value would have to be 18.7v. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the ltc1196/ ltc1198 have one capacitive switching input current spike per conversion. these current spikes settle quickly and do not cause a problem. however, if source resis- tances larger than 100 w are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. + input settling the input capacitor of the ltc1196 is switched onto + input at the end of the conversion and samples the input signal until the conversion begins (see figure 1). the input capacitor of the ltc1198 is switched onto + input during the sample phase (t smpl , see figure 7). the sample phase is 2.5 clk cycles before conversion starts. the voltage on the + input must settle completely within t smpl for the ltc1196/ltc1198. minimizing r source + will improve the input settling time. if a large + input source resis- tance must be used, the sample time can be increased by allowing more time between conversions for the ltc1196 or by using a slower clk frequency for the ltc1198. figure 7. ltc1198 + and C input settling windows clk d in d out ??input ?input sample hold ??input must settle during this time t smpl t conv cs start sgl/diff dummy don? care 1st bit test ?input must settle during this time b7 1196/98 f07 odd/sign dummy
20 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio C input settling at the end of the t smpl , the input capacitor switches to the C input and conversion starts (see figures 1 and 7). during the conversion, the + input voltage is effectively held by the sample-and-hold and will not affect the conversion result. however, it is critical that the C input voltage settle completely during the first clk cycle of the conversion time and be free of noise. minimizing r source C will improve settling time. if a large C input source resistance must be used, the time allowed for settling can be extended by using a slower clk frequency. input op amps when driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see figures 1 and 7). again, the + and C input sampling times can be extended as described above to accommodate slower op amps. to achieve the full sampling rate, the analog input should be driven with a low impedance source (<100 w ) or a high speed op amp (e.g., the lt1223, lt1191, or lt1226). higher impedance sources or slower op amps can easily be accommodated by allowing more time for the analog input to settle as described above. source resistance the analog inputs of the ltc1196/ltc1198 look like a 25pf capacitor (c in ) in series with a 120 w resistor (r on ) as shown in figure 8. c in gets switched between the selected + and C inputs once during each conversion cycle. large external source resistors will slow the settling of the inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle within t smpl . figure 8. analog input equivalent circuit reference input the voltage on the reference input of the ltc1196 defines the voltage span of the a/d converter. the reference input has transient capacitive switching currents which are due to the switched-capacitor conversion technique (see fig- ure 9). during each bit test of the conversion (every clk cycle), a capacitive current spike will be generated on the reference pin by the adc. these high frequency current spikes will settle quickly and do not cause a problem if the reference input is bypassed with at least a 0.1 m f capacitor. the reference input can be driven with standard voltage references. bypassing the reference with a 0.1 m f capacitor is recommended to keep the high frequency impedance low as described above. some references require a small resistor in series with the bypass capacitor for frequency stability. see the individual reference data sheet for details. figure 9. reference input equivalent circuit reduced reference operation the minimum reference voltage of the ltc1198 is limited to 2.7v because the v cc supply and reference are inter- nally tied together. however, the ltc1196 can operate with reference voltages below 1v. the effective resolution of the ltc1196 can be increased by reducing the input span of the converter. the ltc1196 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of linearity and full- scale error vs reference voltage). however, care must be taken when operating at low values of v ref because of the reduced lsb step size and the resulting higher accuracy requirement placed on the converter. the following factors must be considered when operating at low v ref values. 1. offset 2. noise r on 120 w c in 25pf ltc1196 ltc1198 ?? input r source + v in + ? input r source v in ? 1196/98 f08 - t smpl t smpl r on 5pf to 30pf ltc1196 ref + r out v ref every clk cycle 5 4 gnd 1196/98 f09
21 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio offset with reduced v ref the offset of the ltc1196 has a larger effect on the output code when the adc is operated with reduced reference voltage. the offset (which is typically a fixed voltage) becomes a larger fraction of an lsb as the size of the lsb is reduced. the typical curve of unadjusted offset error vs reference voltage shows how offset in lsbs is related to reference voltage for a typical value of v os . for example, a v os of 2mv which is 0.1lsb with a 5v reference becomes 0.5lsb with a 1v reference and 2.5lsb with a 0.2v reference. if this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the C input of the ltc1196. noise with reduced v ref the total input referred noise of the ltc1196 can be reduced to approximately 2mv p-p using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. this noise is insignificant with a 5v reference but will become a larger fraction of an lsb as the size of the lsb is reduced. for operation with a 5v reference, the 2mv noise is only 0.1lsb peak-to-peak. in this case, the ltc1196 noise will contribute virtually no uncertainty to the output code. however, for reduced references, the noise may become a significant fraction of an lsb and cause undesirable jitter in the output code. for example, with a 1v reference, this same 2mv noise is 0.5lsb peak-to- peak. this will reduce the range of input voltages over which a stable output code can be achieved by 1lsb. if the reference is further reduced to 200mv, the 2mv noise becomes equal to 2.5lsb and a stable code is difficult to achieve. in this case averaging readings is necessary. this noise data was taken in a very clean setup. any setup induced noise (noise or ripple on v cc , v ref or v in ) will add to the internal noise. the lower the reference voltage to be used, the more critical it becomes to have a clean, noise- free setup. dynamic performance the ltc1196/ltc1198 have exceptionally high speed sampling capability. fast fourier transform (fft) test techniques are used to characterize the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using a fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figure 10 shows a typical ltc1196 fft plot. figure 10. ltc1196 non-averaged, 4096 point fft plot signal-to-noise ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other fre- quency components at the adcs output. the output is band limited to frequencies above dc and below one half the sampling frequency. figure 10 shows a typical spec- tral content with a 882khz sampling rate. effective number of bits the effective number of bits (enobs) is a measurement of the resolution of an adc and is directly related to s/(n + d) by the equation: n = [s/(n + d) C1.76]/6.02 where n is the effective number of bits of resolution and s/(n + d) is expressed in db. at the maximum sampling frequency (khz) 0 0 10 20 30 40 50 60 70 80 90 100 400 1196/98 g25 100 200 300 500 v cc = 5v f in = 29khz f smpl = 882khz magnitude (db)
22 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer func- tion can create distortion products at sum and difference frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a + f b ) and (f a C f b ) while 3rd order imd terms include (2f a + f b ), (2f a C f b ), (f a + 2f b ), and (f a C 2f b ). if the two input sine waves are equal in magnitudes, the value (in db) of the 2nd order imd products can be expressed by the following formula: imd f f mplitude f f ab ab () = () ? ? 20log a amplitude at f a for input frequencies of 499khz and 502khz, the imd of the ltc1196/ltc1198 is 51db with a 5v supply. peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spec- tral component excluding the input signal and dc. this value is expressed in dbs relative to the rms value of a full- scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is re- duced by 3db for a full-scale input. the full-linear bandwidth is the input frequency at which the effective bits rating of the adc falls to 7 bits. beyond this frequency, distortion of the sampled input signal increases. the ltc1196/ltc1198 have been designed to optimize input bandwidth, allowing the adcs to undersample input signals with frequencies above the converters nyquist frequency. rate of 1.2mhz with a 5v supply the ltc1196 maintains above 7.5 enobs at 400khz input frequency. above 500khz the enobs gradually decline, as shown in figure 11, due to increasing second harmonic distortion. the noise floor remains low. figure 11. effective bits and s/(n + d) vs input frequency total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half of the sampling frequency. thd is defined as: thd = ++++ 20log vvv v v 2 2 3 2 4 2 n 2 1 ... where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through the n th harmonics. the typical thd speci- fication in the dynamic accuracy table includes the 2nd through 5th harmonics. with a 100khz input signal, the ltc1196/ltc1198 have typical thd of 50db and 49db with v cc = 5v and v cc = 3v, respectively. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can input frequency (hz) 1k s/(n + d) (db) 8 7 6 5 4 3 2 1 0 10k 100k 1m 1196/98 g24 50 44 effective number of bits (enobs) v ref = v cc = 2.7v f smpl = 383khz (ltc1196) f smpl = 287khz (ltc1198) v ref = v cc = 5v f smpl = 1mhz (ltc1196) f smpl = 750khz (ltc1198) t a = 25?
23 ltc1196/ltc1198 u s a o pp l ic at i wu u i for atio 3v versus 5v performance comparison table 1 shows the performance comparison between 3v and 5v supplies. the power dissipation drops by a factor of five when the supply is reduced to 3v. the converter slows down somewhat but still gives excellent perfor- mance on a 3v rail. with a 3v supply, the ltc1196 converts in 1.6 m s, samples at 450khz, and provides a 500khz linear-input bandwidth. dynamic accuracy is excellent on both 5v and 3v. the adcs typically provide 49.3db of 7.9 enobs of dynamic accuracy at both 3v and 5v. the noise floor is extremely low, corresponding to a transition noise of less than 0.1lsb. dc accuracy includes 0.5lsb total unadjusted error at 5v. at 3v, linearity error is 0.5lsb while total unadjusted error increases to 1lsb. table 1. 5v/3v performance comparison ltc1196-1 5v 3v p diss 50mw 10mw max f smpl 1mhz 383khz min t conv 600ns 1.6 m s inl (max) 0.5lsb 0.5lsb typical enobs 7.9 at 300khz 7.9 at 100khz linear input bandwidth (enobs > 7) 1mhz 500khz ltc1198-1 p diss 50mw 10mw p diss (shutdown) 15 m w9 m w max f smpl 750khz 287khz min t conv 600ns 1.6 m s inl (max) 0.5lsb 0.5lsb typical enobs 7.9 at 300khz 7.9 at 100khz linear input bandwidth (enobs > 7) 1mhz 500khz u s a o pp l ic at i ty p i ca l pld interface using the altera epm5064 the altera epm5064 has been chosen to demonstrate the interface between the ltc1196 and a pld. the epm5064 is programmed to be a 12-bit counter and an equivalent 74hc595 8-bit shift register as shown in figure 12. the circuit works as follows: bringing ena high makes the cs output high and the en input low to reset the ltc1196 and disable the shift register. bringing ena low, the cs output goes high for one clk cycle with every 12 clk cycles. the inverted signal, en, of the cs output makes the 8-bit data available on the b0-b7] lines. figures 13 and 14 show the interconnection between the ltc1196 and epm5064 and the timing diagram of the signals between these two devices. the clk frequency in this circuit can run up to f clk(max) of the ltc1196. 1196/98 f12 data clk 12-bit converter cs ena en clk b0-b7 8-bit shift register cs ena clk data b0-b7 figure 12. an equivalent circuit of the epm5064 figure 13. intefacing the ltc1196 to the altera epm5064 pld 3, 14, 25, 36 epm5064 clk 33 23 34 35 1196/98 f13 v cc + data 1 37 38 39 40 41 42 44 9-13, 21, 31, 32, 43 clk b7 b0 ena ?n gnd v cc clk d out +in cs 1 2 3 4 8 7 6 5 ltc1196 v ref 1 m f reserve pins of epm5064: 2, 4-8,15-20, 22, 24, 26-30
24 ltc1196/ltc1198 figure 14. the timing diagram u s a o pp l ic at i ty p i ca l the ltc1198 in figure 15 can be 2.7v to 6v with f clk = 5mhz. at 2.7v, f clk = 5mhz will work at 25 c. see recommended operating conditions for limits over tem- perature. hardware description the circuit works as follows: the ltc1198 clock line controls the a/d conversion rate and the data shift rate. data is transferred in a synchronous format over d in and d out . the serial port of the tms320c25 is compatible with that of the ltc1198. the data shift clock lines (clkr, clkx) are inputs only. the data shift clock comes from an external source. inverting the shift clock is necessary because the ltc1198 and the tms320c25 clock the input data on opposite edges. the schematic of figure 15 is fed by an external clock source. the signal is fed into the clk pin of the ltc1198 directly. the signal is inverted with a 74hc04 and then applied to the data shift clock lines (clkr, clkx). the framing pulse of the tms320c25 is fed directly to the cs of the ltc1198. dx and dr are tied directly to d in and d out respectively. interfacing the ltc1198 to the tms320c25 dsp figure 15 illustrates the interface between the ltc1198 8-bit data acquisition system and the tms320c25 digital signal processor (dsp). the interface, which is optimized for speed of transfer and minimum processor supervi- sion, can complete a conversion and shift the data in 4 m s with f clk = 5mhz. the cycle time, 4 m s, of each conversion is limited by maximum clock frequency of the serial port of the tms320c25 which is 5mhz. the supply voltage for figure 15. interfacing the ltc1198 to the tms320c25 dsp 1196/98 f15 5mhz clk clkx clkr fsr fsx dx dr clk ltc1198 tms320c25 cs d in d out ch0 ch1 70 140 210 280 350 420 490 560 630 700 770 840 910 980 1050 1120 data clk cs b7 b4 b6 b5 b3 b1 b2 b0 time (ns) 1196/98 f14
25 ltc1196/ltc1198 u s a o pp l ic at i ty p i ca l software description the software configures and controls the serial port of the tms320c25. the code first sets up the interrupt and reset vectors. on reset the tms320c25 starts executing code at the label init. upon completion of a 16-bit data transfer, an inter- rupt is generated and the dsp will begin executing code at the label rint. in the beginning, the code initializes registers in the tms320c25 that will be used in the transfer routine. the interrupts are temporarily disabled. the data memory page pointer register is set to zero. the auxiliary register pointer is loaded with one and auxiliary register one is loaded with the value 200 hexadecimal. this is the data memory location where the data from the ltc1198 will be stored. the interrupt mask register (imr) is configured to recognize the rint interrupt, which is generated after receiving the last of 16 bits on the serial port. this interrupt is still disabled at this time. the transmit framing synchro- nization pin (fsx) is configured to be an output. the f0 bit of the status register st1, is initialized to zero which sets up the serial port to operate in the 16-bit mode. next, the code in txrx routine starts to transmit and receive data. the d in word is loaded into the acc and shifted left eight times so that it appears as in figure 18. this d in word configures the ltc1198 for ch0 with respect to ch1. the d in word is then put in the transmit register and the rint interrupt is enabled. the nop is repeated 3 times to mask out the interrupts and minimize the cycle time of the conversion to be 20 clock cycles. all clocking and cs functions are performed by the hardware. the timing diagram of figure 16 was obtained from the circuit of figure 15. the clk was 5mhz for the timing diagram and the tms320c25 clock rate was 40mhz. figure 17 shows the timing diagram with the ltc1198 running off a 2.7v supply and 5mhz clk. cs clk d in figure 16. scope trace the ltc1198 running off 5v supply in the circuit of figure 15 cs clk d in vertical: 5v/div vertical: 5v/div figure 18. d in word in acc of tms320c25 for the circuit in figure 15 horizontal: 1500ns/div 1196/98 f16 lsb (b0) horizontal: 500ns/div 1196/98 f17 figure 17. scope trace the ltc1198 running off 2.7v supply in the circuit of figure 15 null bits msb (b7) lsb (b0) null bits msb (b7) l1196/98 f18 b15 b8 0 1 start 0 s/d 0 o/s 0 dummy 1 dummy 0 0 d out d out
26 ltc1196/ltc1198 u s a o pp l ic at i ty p i ca l once rint is generated the code begins execution at the label rint. this code stores the d out word from the ltc1198 in the acc and then stores it in location 200 hex. the data appears in location 200 hex right-justified as shown in figure 19. the code is set up to continually loop, so at this point the code jumps to label txrx and repeats from here. l1196/98 f19 msb lsb x x x x x x x x 7 6 5 4 3 2 1 0 d out from ltc1198 stored in tms320c25 ram > 200 figure 19. memory map for the circuit in figure 15 label mnemonic comments aorg 0 on reset code execution starts at 0 b init branch to initialization routine aorg >26 address of rint interrupt vector b rint branch to rint service routine aorg >32 main program starts here init dint disable interrupts ldpk >0 set data memory page pointer to 0 larp >1 set auxiliary register pointer to 1 lrlk ar1,>200 set auxiliary register 1 to >200 lack >10 load imr config word into acc sacl >4 store imr config word into imr stxm configure fsx as an output fort 0 set serial port to 16-bit mode txrx lack >44 load ltc1198 d in word into acc sfsm fsx pulses generated on xsr load rptk 7 repeat next instruction 8 times sfl shifts d in word to right position sacl >1 put d in word in transmit register eint enable interrupt (disabled on rint) rptk 2 minimize the conversion cycle time nop to be 20 clock cycles rint zals >0 store ltc1198 dout word in acc sacl *, 0 store acc in location >200 b txrx branch to transmit receive routine end figure 20. tms320c25 code for the circuit in figure 15
27 ltc1196/ltc1198 package descriptio u dimension in inches (millimeters) unless otherwise noted. information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. s8 package 8-lead plastic soic 1 2 3 4 0.150 ?0.157 (3.810 ?3.988) 8 7 6 5 0.189 ?0.197 (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 8?typ 0.008 ?0.010 (0.203 ?0.254) so8 0493 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc
28 ltc1196/ltc1198 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7487 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 lt/gp 0893 10k rev 0 ? printed in usa ? linear technology corporation 1993 northeast region linear technology corporation one oxford valley 2300 e. lincoln hwy.,suite 306 langhorne, pa 19047 phone: (215) 757-8578 fax: (215) 757-5631 linear technology corporation 266 lowell st., suite b-8 wilmington, ma 01887 phone: (508) 658-3881 fax: (508) 658-2701 u.s. area sales offices southeast region linear technology corporation 17060 dallas parkway suite 208 dallas, tx 75248 phone: (214) 733-3071 fax: (214) 380-5138 central region linear technology corporation chesapeake square 229 mitchell court, suite a-25 addison, il 60101 phone: (708) 620-6910 fax: (708) 620-6977 southwest region linear technology corporation 22141 ventura blvd. suite 206 woodland hills, ca 91364 phone: (818) 703-0835 fax: (818) 703-0517 northwest region linear technology corporation 782 sycamore dr. milpitas, ca 95035 phone: (408) 428-2050 fax: (408) 432-6331 france linear technology s.a.r.l. immeuble "le quartz" 58 chemin de la justice 92290 chatenay malabry france phone: 33-1-41079555 fax: 33-1-46314613 germany linear techonolgy gmbh untere hauptstr. 9 d-85386 eching germany phone: 49-89-3197410 fax: 49-89-3194821 international sales offices japan linear technology kk 5f yz bldg. 4-4-12 iidabashi, chiyoda-ku tokyo, 102 japan phone: 81-3-3237-7891 fax: 81-3-3237-8010 korea linear technology korea branch namsong building, #505 itaewon-dong 260-199 yongsan-ku, seoul korea phone: 82-2-792-1617 fax: 82-2-792-1619 singapore linear technology pte. ltd. 101 boon keng road #02-15 kallang ind. estates singapore 1233 phone: 65-293-5322 fax: 65-292-0398 taiwan linear technology corporation rm. 801, no. 46, sec. 2 chung shan n. rd. taipei, taiwan, r.o.c. phone: 886-2-521-7575 fax: 886-2-562-2285 united kingdom linear technology (uk) ltd. the coliseum, riverside way camberley, surrey gu15 3yl united kingdom phone: 44-276-677676 fax: 44-276-64851 world headquarters linear technology corporation 1630 mccarthy blvd. milpitas, ca 95035-7487 phone: (408) 432-1900 fax: (408) 434-0507 08/16/93

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